A design methodology for the automatic sizing of standard-cell libraries

Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, there are opposite trends to compact and extend the standard cell libraries, and to move towards custom libraries, highly optimized for specific goals (e.g., area, timing or power consumption) or designs. We thus propose a design methodology for library sizing that combines decimation strategies and generation of cell variants. The proposed methodology is based on Simulated Annealing, also integrating heuristic principles to efficiently guide the exploration process. The approach has been validated on a set of common benchmarks for logic synthesis, demonstrating interesting results, specially when starting from a relative small initial library.