Area impact analysis of via-configurable regular fabric for digital integrated circuit design

Transistor regular layout (TRL) has been considered a more lithography-reliable approach for digital integrated circuit design than the most conventional standard cell design. However, the impact in circuit area seems to be unavoidable due to the loss in design flexibility. Hence, the decision in applying such design strategy depends not only on the expected yield improvement but also on the careful evaluation of circuit penalty. This paper presents an extensive analysis and discussion about area impact of TRL design style in comparison to the standard cell one. Several benchmark circuits were mapped by addressing specific cell libraries built for this purpose. Experimental results demonstrated that efficient TRL templates may minimize significantly the area overhead.