Multiple-step process window aware OPC for hyper-NA lithography

To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.