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2010•Unpublished venueRequires access

Mobility enhancement in silicon nanowire transistors

Toshiro Hiramoto, Jiezhi Chen, Takuya Saraya

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Abstract

Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while electron mobility degradation is minimized in nanowire nFET. Underlying physical mechanisms are discussed.

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What this paper is about

Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while electron mobility degradation is minimized in nanowire nFET. Underlying physical mechanisms are discussed.

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Available abstract

Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while electron mobility degradation is minimized in nanowire nFET. Underlying physical mechanisms are discussed.

Key concepts: Nanowire, Materials science, Electron mobility, Silicon nanowires, Optoelectronics, Silicon, Silicon on insulator, Transistor

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