A switch architecture and signal synchronization for GALS system-on-chips

Increasing power consumption and growing design effort are considered limiting factors in the design of chip-wide synchronous System-on-Chip designs. The attempt to get over these problems leads to an intensified look at asynchronous communication solutions, sometimes based on Network-on-Chips. Despite this basically asynchronous approach, most of the actual research work is not supporting a globally genuinely-asynchronous solution. We present a modular switch for a true globally asynchronous interconnect network. Independent clock generators in each switch maintain a local clock thus avoiding a global clock at the level of the interconnect network. The general switch architecture is described and the integration of the synchronization technique used to resolve metastability is discussed in detail. First synthesis results of a prototypical VLSI implementation are presented.