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2014•Unpublished venueRequires access

A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking

Yan Lü, Ruo He Yao, Da Qiang Huang, Julien Su, Junmin Jiang, Wing‐Hung Ki

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Abstract

This paper presents a low-dropout regulator (LDO) with low quiescent current, small area, and power supply rejection (PSR) improvement, implemented in 0.35μm CMOS process. A zero that tracks the unity gain frequency is employed in the feedback loop using a 1pF compensation capacitor. An improved intermediate stage is designed to split the low frequency pole and drive the power MOSFET. With no equivalent series resistor (ESR) zero requirement, the minimum DC gain and phase margin are 76dB and 70°, respectively. The proposed LDO dissipates 20μA at no-load condition and 385μA at full-load condition. The effective die area is 180×75μm2that is comparable to the size of a standard I/O. Thus, integrating the proposed LDO in system is flexible.

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What this paper is about

This paper presents a low-dropout regulator (LDO) with low quiescent current, small area, and power supply rejection (PSR) improvement, implemented in 0.35μm CMOS process. A zero that tracks the unity gain frequency is employed in the feedback loop using a 1pF compensation capacitor. An improved intermediate stage is designed to split the low frequency pole and drive the power MOSFET. With no equivalent series resistor (ESR) zero requirement, the minimum DC gain and phase margin are 76dB and 70°, respectively. The proposed LDO dissipates 20μA at no-load condition and 385μA at full-load condition. The effective die area is 180×75μm2that is comparable to the size of a standard I/O. Thus, integrating the proposed LDO in system is flexible.

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Available abstract

This paper presents a low-dropout regulator (LDO) with low quiescent current, small area, and power supply rejection (PSR) improvement, implemented in 0.35μm CMOS process. A zero that tracks the unity gain frequency is employed in the feedback loop using a 1pF compensation capacitor. An improved intermediate stage is designed to split the low frequency pole and drive the power MOSFET. With no equivalent series resistor (ESR) zero requirement, the minimum DC gain and phase margin are 76dB and 70°, respectively. The proposed LDO dissipates 20μA at no-load condition and 385μA at full-load condition. The effective die area is 180×75μm2that is comparable to the size of a standard I/O. Thus, integrating the proposed LDO in system is flexible.

Key concepts: Phase margin, Low-dropout regulator, Frequency compensation, Capacitor, Control theory (sociology), Bandwidth (computing), Resistor, Regulator

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