Threshold voltage modelling and gate oxide thickness effect on polycrystalline silicon thin-film transistors

This paper presents an analytical model for calculating the threshold voltage in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with large grains. In the present study, it is assumed that the oxide-silicon interface traps are uniformly distributed and the channel of the device contains only a single grain boundary. Further, the effect of gate oxide thickness on threshold voltage and hence on transfer characteristics has also been incorporated in this paper. It is observed that scaling down of the oxide thickness is an efficient way to reduce the threshold voltage and hence to improve the poly-Si TFT characteristics at different temperatures and trap densities. The results so obtained are compared with the available experimental data which show a satisfactory match thus justifying the validity of the model.