An expression for the propagation delay of a differential split-level (DSL) CMOS logic gate

The propagation delay of logic circuits are usually predicted with complex and time-consuming simulation programs. However, based on static analysis techniques, an expression for the propagation delay of a differential split-level CMOS logic gate has been derived. Variables in the expression are functions of geometrical, electrical, and technological parameters. Propagation delays calculated with this expression correspond to those obtained using simulation programs.