Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.