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2012•International Journal of Scientific ResearchOpen access

Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL

Hitesh G Kamani

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Abstract

In this paper design of Reed Solomon (255,239) Encoder and Decoder and perform this Codec on family of Cyclone FPGA and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. I applied forward error correction system to improve the overall performance of the system. The implementation is Written in VHDL based on Barlekamp Massy, Forney and Chien Search Algorithm. Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL

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What this paper is about

In this paper design of Reed Solomon (255,239) Encoder and Decoder and perform this Codec on family of Cyclone FPGA and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. I applied forward error correction system to improve the overall performance of the system. The implementation is Written in VHDL based on Barlekamp Massy, Forney and Chien Search Algorithm. Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL

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Available abstract

In this paper design of Reed Solomon (255,239) Encoder and Decoder and perform this Codec on family of Cyclone FPGA and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. I applied forward error correction system to improve the overall performance of the system. The implementation is Written in VHDL based on Barlekamp Massy, Forney and Chien Search Algorithm. Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL

Key concepts: VHDL, Field-programmable gate array, Encoder, Cyclone (programming language), Computer science, Embedded system, Computer hardware, Operating system

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