Design of area and power efficient complex number multiplier

Complex number multiplication is one of the most important arithmetic operations in signal processing. The paper proposes a design of high speed 8-bit complex number multiplier where the multiplication process is carried out using Vedic Mathematics [1], Urdhva Tiryagbhyam (Vertically and Cross-wise) sutra and the addition achieved by use of modified adder architectures to reduce the area occupied and power dissipated. Multiplication is realized using modified 8-bit multipliers [2]. The proposed 8-bit multiplier [2] results in a 6.23% increase in speed, 1.88% decrease in area and 13.84% decrease in power dissipation when compared to the normal 8-bit Vedic multiplier. Further, the proposed 8-bit complex number multiplier results in a 9.11% decrease in power dissipated when compared to the normal 8-bit complex number Vedic multiplier.