The design and verification of packet processing engine model using SystemC

The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC language, and use the SystemC language for the system-level modeling of the packet processing engine. In addition an independent simulation model is built, and the performance of packet processing engine is analyzed and verificated. Compared with the traditional hardware description language model we can obtain about 1.5 times simulation speed as much as that of HDL model.