Improving Threshold Voltage and Device Performance of Gate-First HfSiON/Metal Gate n-MOSFETs by an ALD La[sub 2]O[sub 3] Capping Layer

We have studied the effect on the electrical properties of depositing Lanthanum-oxide ( La 2 O 3 ) capping layers on Hafnium-silicon-oxynitride ( HfSiON ) /Tantalum-silicon-nitride ( TaSiN ) metal gate first stacks. The capping layers were deposited by atomic layer deposition (ALD) using a La ( i - PrCp ) 3 precursor and ozone. The capacitance voltage characteristics shifted negatively by a significant amount with increasing numbers of ALD - La 2 O 3 cycles, and the shifts in the flatband voltage ( V FB ) with 10 ALD cycles were ∼ 500 mV for gate stacks with Hf ∕ ( Hf + Si ) compositions of 56 and 74%. An equivalent oxide thicknesses (EOT) of ∼ 0.7 nm was obtained for the HfSiON gate stack with Hf ∕ ( Hf + Si ) composition of 74% with a La 2 O 3 capping layer. Postdeposition annealing at 1050°C caused Lanthanum diffusion into the HfSiON ∕ SiON gate stack, forming La – O bonds at the Hf ( La ) SiON ∕ Si ( La ) ON interface, and increasing the dielectric constant. The threshold voltage ( V th ) achieved with two ALD - La 2 O 3 cycles and the 56% Hf ∕ ( Hf + Si ) composition gate stack was ∼ 0.3 V , almost the same as that for 1.8 nm SiO 2 /n-Poly Si devices. The drain current ( I d ) at V g = + 1.1 V improved dramatically with the increasing number of ALD cycles, with values twice as large for devices capped with La 2 O 3 compared to those with bare HfSiON gate stacks (noncapped samples). The EOTs and gate leakage current densities clearly meet the criteria for half pitch 32 nm metal gate bulk devices in the International Technology Roadmap for Semiconductor 2006.