2007CAS proceedingsRequires access

A Single Poly CMOS Process Evaluation for Floating Gate Applications

M. Bădilă, T. Dunca, P. Cosmin

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Abstract

The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.

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What this paper is about

The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.

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Available abstract

The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.

Key concepts: EEPROM, CMOS, Process (computing), EPROM, Computer science, Electronic engineering, Electrical engineering, Logic gate

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