A Single Poly CMOS Process Evaluation for Floating Gate Applications
M. Bădilă, T. Dunca, P. Cosmin
Abstract
M. Bădilă, T. Dunca, P. Cosmin
Abstract
The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.
A significance statement is not available in the OpenAlex record.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.
Key concepts: EEPROM, CMOS, Process (computing), EPROM, Computer science, Electronic engineering, Electrical engineering, Logic gate