ScholarLens Back to search
2007•Unpublished venueRequires access

RFIC Design Methodology: Functional Verification

William Dunham

Open publisher page 0 citations

Abstract

Full-chip functional verification for RF-A/MS (analog mixed-signal) applications is not only new as a "design methodology process" to some design organizations; but, is fast becoming a "must have" verification as a final tape-out simulation sign-off. Today's wireless industry, due to tight schedule demands and short product life-cycles, requires that a RFIC development group deliver "1stpass functional silicon." Then, when functional RFIC silicon is produced, minor design changes (minimal mask-layer changes) needed to meet performance specifications can be accommodated within a wireless product schedule.

About this research paper

What this paper is about

Full-chip functional verification for RF-A/MS (analog mixed-signal) applications is not only new as a "design methodology process" to some design organizations; but, is fast becoming a "must have" verification as a final tape-out simulation sign-off. Today's wireless industry, due to tight schedule demands and short product life-cycles, requires that a RFIC development group deliver "1stpass functional silicon." Then, when functional RFIC silicon is produced, minor design changes (minimal mask-layer changes) needed to meet performance specifications can be accommodated within a wireless product schedule.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Full-chip functional verification for RF-A/MS (analog mixed-signal) applications is not only new as a "design methodology process" to some design organizations; but, is fast becoming a "must have" verification as a final tape-out simulation sign-off. Today's wireless industry, due to tight schedule demands and short product life-cycles, requires that a RFIC development group deliver "1stpass functional silicon." Then, when functional RFIC silicon is produced, minor design changes (minimal mask-layer changes) needed to meet performance specifications can be accommodated within a wireless product schedule.

Key concepts: RFIC, Schedule, Computer science, Integrated circuit design, Product (mathematics), Wireless, Process (computing), Chip

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
RFIC Design Methodology: Functional Verification — Research Paper | ScholarLens