2012•Unpublished venueRequires access

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

Chau‐Jie Zhan, Pei-Jer Tzeng, John H. Lau, Ming-Ji Dai, Heng-Chieh Chien, Ching-Kuan Lee, Shang-Tsai Wu, Kuo‐Shu Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu‐Wei Huang, Yu-Min Lin, Jing‐Yao Chang, Tsung‐Fu Yang, Tai‐Hung Chen, Robert Lo, Ming‐Jer Kao

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Abstract

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

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Available abstract

Key concepts: Interposer, System in package, Reliability (semiconductor), Three-dimensional integrated circuit, Stacking, Chip, Integrated circuit packaging, Through-silicon via