The Soft-Injection-Locked Ring Oscillator and Its Application in a Vernier-Based TDC
Chia-Yu Yao, Wei‐Chun Hsia, Yu-Jou Wen
Abstract
Chia-Yu Yao, Wei‐Chun Hsia, Yu-Jou Wen
Abstract
A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based TDC (VTDC) is promising because the time resolution of it depends on the frequency difference between the oscillators, not on the absolute oscillating frequency values. However, the oscillators used in the conventional VTDC require complicated calibration procedures. This makes the TDC system complex. This paper employs a new soft-injection-locked ring oscillator as the clock source for the VTDC. The proposed oscillator can oscillate immediately and accurately right after the triggering signal arrives. The TDC structure employing the purposed oscillators is verified by the TSMC 0.18μm CMOS process. The measured differential nonlinearity is within ±0.4 LSB and the measured integral nonlinearity is within ±0.8 LSB. The power consumption is 27.8 mW. The chip's core area is around 0.095 mm2. When the supply voltage varies from 1.75 to 1.85 V, the resolution deviation is less than ±0.18 LSB.
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A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based TDC (VTDC) is promising because the time resolution of it depends on the frequency difference between the oscillators, not on the absolute oscillating frequency values. However, the oscillators used in the conventional VTDC require complicated calibration procedures. This makes the TDC system complex. This paper employs a new soft-injection-locked ring oscillator as the clock source for the VTDC. The proposed oscillator can oscillate immediately and accurately right after the triggering signal arrives. The TDC structure employing the purposed oscillators is verified by the TSMC 0.18μm CMOS process. The measured differential nonlinearity is within ±0.4 LSB and the measured integral nonlinearity is within ±0.8 LSB. The power consumption is 27.8 mW. The chip's core area is around 0.095 mm2. When the supply voltage varies from 1.75 to 1.85 V, the resolution deviation is less than ±0.18 LSB.
Key concepts: Vernier scale, Differential nonlinearity, Integral nonlinearity, Ring oscillator, Time-to-digital converter, CMOS, Voltage, Electronic engineering