2011Journal of SemiconductorsRequires access

A 8.75–11.2-GHz, low phase noise fractional-Nsynthesizer for 802.11a/b/g zero-IF transceiver

Niansong Mei, Yaohua Pan, Yumei Huang, Zhiliang Hong

Open publisher page 1 citations

Abstract

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer's spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement results exhibits that the frequency synthesizer's integrated phase noise is less than 1° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below −60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

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What this paper is about

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer's spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement results exhibits that the frequency synthesizer's integrated phase noise is less than 1° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below −60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

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Available abstract

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer's spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement results exhibits that the frequency synthesizer's integrated phase noise is less than 1° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below −60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

Key concepts: Frequency synthesizer, dBc, Phase noise, Direct digital synthesizer, Transceiver, Electrical engineering, CMOS, Phase-locked loop

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