A 12-Bit 33-mW and 96-MHz Discrete-Time Sigma Delta ADC in 130 nm CMOS Technology

The paper presents a 12-bit discrete-time third-order Sigma Delta analog-to-digital converter (ADC) for Sub-GHz transceiver applications. In the designed ADC, a sigma delta modulator with 74.76 dB SNR was implemented. The modulator consumes approximate 33 mW from a 3.3 V supply and operates at sampling frequency of 96 MHz with an oversampling ratio of 64. Digital decimation filter including CIC filter and FIR filter is integrated with the analog sigma delta modulator for the full ADC operation. The filter achieves a cut-off frequency of 750kHz and operates at a data rate of 12 Msps or 6 Msps. The ADC circuit has been implemented using 130 nm CMOS technology. At a supply voltage of 3.3 V, the maximum ENOB is simulated to be 12.12 bit which corresponds to a resolution of 12 bit. The simulations on each corner confirm that the modulator satisfies the specifications even in the worst case.