2002•Unpublished venueRequires access
Analysis of the switching characteristics of NMOS common drain FET logic (CDFL)
Y.J. Maa, Ibrahim Abdel‐Motaleb
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Abstract
The switching characteristics of a novel NMOS structure, the common drain FET logic (CDFL) is studied. A technique utilizing a load capacitor charging and discharging mechanism to calculate the output waveform of NMOS CDFL buffer and DCFL (direct coupled FET logic) inverter has been used. The results show that a CDFL buffer can be at least twice as fast as a DCFL inverter occupying the same area. Using the buffer to build positive logic gates and the inverter to build negative logic gates leads to at least at 100% increase in the speed of the overall circuit and a 33% decrease in the occupied area.>