2018IEEE Electron Device LettersRequires access

Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study

Saptak Banerjee, Shelly Garg, Sneh Saurabh

Open publisher page 32 citations

Abstract

In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to realize different logic functions and investigated using two-dimensional device simulations. It is shown that a single DGTFET can realize logic functions, such as AND, OR, NAND, and NOR by biasing the two gates independently. The key elements in obtaining different logic functions using a DGTFET are employing a gate-source overlap and choosing an appropriate silicon body thickness. Furthermore, it is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.

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What this paper is about

In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to realize different logic functions and investigated using two-dimensional device simulations. It is shown that a single DGTFET can realize logic functions, such as AND, OR, NAND, and NOR by biasing the two gates independently. The key elements in obtaining different logic functions using a DGTFET are employing a gate-source overlap and choosing an appropriate silicon body thickness. Furthermore, it is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.

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OpenAlex reports 32 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to realize different logic functions and investigated using two-dimensional device simulations. It is shown that a single DGTFET can realize logic functions, such as AND, OR, NAND, and NOR by biasing the two gates independently. The key elements in obtaining different logic functions using a DGTFET are employing a gate-source overlap and choosing an appropriate silicon body thickness. Furthermore, it is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.

Key concepts: NAND gate, Logic gate, AND-OR-Invert, NMOS logic, Pass transistor logic, NAND logic, NOR logic, Logic family

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