High slew-rate, high gain operational amplifier driving large capacitive loads in a BiCMOS high voltage technology

This paper describes the design and implementation of a high slew rate, high gain Operational Amplifier in a 3 /spl mu/m high voltage BiCMOS process. A BiCMOS differential pair and an inverter gain stage with P-MOS cascode load is used in order to achieve a slew rate of about 50 V//spl mu/s and a DC open loop gain of 112 dB. A novel BiCMOS output buffer which can drive capacitive loads from 0 to 200 pF is introduced. A comparison between the proposed amplifier and two amplifiers available in the cell library of the used technology is presented: it demonstrates the excellent performance of the proposed amplifier in term of slew rate, capacitance driving capability, open loop DC gain and CMRR.