Influence of the driver and active load threshold voltage in design of pseudo-NMOS logic

During the design phase of different logic gates based on MOS technologies, it is necessary to take into consideration many parameters which characterise MOS transistors. One of the parameters which characterizes all types of MOSFET transistors is the threshold voltage that has impact in static and dynamic performances of the different logic gates. The aim of this paper is to research the impact threshold voltage of NMOS (driver) and PMOS (active load) transistors during the design phase of pseudo-NMOS inverters and in pseudo-NMOS logic gates which perform specific logic functions. The results obtained emphasize the impact of each single value of the threshold voltage at the low level of the output voltage, at the level values of static current at output and on the shape of the voltage transfer characteristic in the pseudo-NMOS inverter and pseudo-NMOS logic gates. By adjusting the threshold voltage values of NMOS and PMOS transistor it's possible to design pseudo-NMOS logic gate which will have acceptable performance depending on designers' requests.