A new low-voltage CMOS 1-bit full adder for high performance applications

In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage design consumes minimal power and has a minimal power-delay product in the TSMC 0.35 /spl mu/m process, as supply voltage varies from 3.3 V to 2 V. Also, the new cell is demonstrated to consume minimal power as adopted in a 4/spl times/4 bit carry-save array adder, and a 4/spl times/4 bit pipelined carry-save array adder.