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An incremental synthesis method for ASIC design

J.-C. Giomi

Open publisher page 4 citations

Abstract

An incremental synthesis method which enables ASIC designers to incrementally modify their register-transfer-level (RTL) behavior descriptions is described. This synthesis method synthesizes and optimizes only RTL behaviors which have been modified. An incremental synthesis approach reduces the overall synthesis time when an incremental modification has been performed. This synthesis method allows ASIC designers to control the design space exploration more closely.>

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What this paper is about

An incremental synthesis method which enables ASIC designers to incrementally modify their register-transfer-level (RTL) behavior descriptions is described. This synthesis method synthesizes and optimizes only RTL behaviors which have been modified. An incremental synthesis approach reduces the overall synthesis time when an incremental modification has been performed. This synthesis method allows ASIC designers to control the design space exploration more closely.>

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

An incremental synthesis method which enables ASIC designers to incrementally modify their register-transfer-level (RTL) behavior descriptions is described. This synthesis method synthesizes and optimizes only RTL behaviors which have been modified. An incremental synthesis approach reduces the overall synthesis time when an incremental modification has been performed. This synthesis method allows ASIC designers to control the design space exploration more closely.>

Key concepts: Application-specific integrated circuit, High-level synthesis, Computer science, Register-transfer level, Control (management), Computer architecture, Logic synthesis, Embedded system

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