PRMC: a multicontext FPGA with partially reconfigurable logic planes
Jason Smith, Tian Xia
Abstract
Jason Smith, Tian Xia
Abstract
Multicontext field programmable gate arrays (FPGAs) are excellent devices to use in reconfigurable computing systems for boosting performance. In addition, multicontext devices can save space compared to the conventional FPGAs because they store more programming data per area. However, multicontext FPGAs suffer the same long configuration delays as conventional FPGAs, and this limits performance in some situations. To solve that problem, we introduce a new FPGA called PRMC. The PRMC FPGA is an enhanced multicontext design that has partially reconfigurable contexts and additional features to reduce the configuration overhead. As a result, PRMC configures faster than present multicontext FPGAs, while enjoying the same area benefit. This paper describes the architecture of our PRMC FPGA.
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Multicontext field programmable gate arrays (FPGAs) are excellent devices to use in reconfigurable computing systems for boosting performance. In addition, multicontext devices can save space compared to the conventional FPGAs because they store more programming data per area. However, multicontext FPGAs suffer the same long configuration delays as conventional FPGAs, and this limits performance in some situations. To solve that problem, we introduce a new FPGA called PRMC. The PRMC FPGA is an enhanced multicontext design that has partially reconfigurable contexts and additional features to reduce the configuration overhead. As a result, PRMC configures faster than present multicontext FPGAs, while enjoying the same area benefit. This paper describes the architecture of our PRMC FPGA.
Key concepts: Field-programmable gate array, Reconfigurable computing, Computer science, Boosting (machine learning), Overhead (engineering), Embedded system, Programmable logic array, Programmable logic device