2015Unpublished venueRequires access

Constant gm rail-to-rail CMOS OpAmp with only one differential pair and switched level shifters

M. R. Valero, Antonio J. López‐Martín, Alejandro Román-Loera, J. Ramı́rez-Angulo, R.G. Carvajal

Open publisher page 2 citations

Abstract

This paper introduces a simple approach for the implementation of rail-to-rail operational amplifiers (OpAmps) with constant gmusing only one differential input pair. It is based on the utilization of switched voltage followers that introduce a DC level shift when the OpAmp's common mode input voltage is lower than the headroom of the input differential pair (DP). Additional circuitry is introduced in order to make the DP tail current insensitive to common mode input voltage variations. This improves CMRR and PSRR and reduces gmvariations. The additional circuitry increases power dissipation by less than 20%. Simulation results are presented that verify rail-to-rail operation with ±1.65 supply voltages in 0.5μm CMOS technology.

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What this paper is about

This paper introduces a simple approach for the implementation of rail-to-rail operational amplifiers (OpAmps) with constant gmusing only one differential input pair. It is based on the utilization of switched voltage followers that introduce a DC level shift when the OpAmp's common mode input voltage is lower than the headroom of the input differential pair (DP). Additional circuitry is introduced in order to make the DP tail current insensitive to common mode input voltage variations. This improves CMRR and PSRR and reduces gmvariations. The additional circuitry increases power dissipation by less than 20%. Simulation results are presented that verify rail-to-rail operation with ±1.65 supply voltages in 0.5μm CMOS technology.

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Available abstract

This paper introduces a simple approach for the implementation of rail-to-rail operational amplifiers (OpAmps) with constant gmusing only one differential input pair. It is based on the utilization of switched voltage followers that introduce a DC level shift when the OpAmp's common mode input voltage is lower than the headroom of the input differential pair (DP). Additional circuitry is introduced in order to make the DP tail current insensitive to common mode input voltage variations. This improves CMRR and PSRR and reduces gmvariations. The additional circuitry increases power dissipation by less than 20%. Simulation results are presented that verify rail-to-rail operation with ±1.65 supply voltages in 0.5μm CMOS technology.

Key concepts: Operational amplifier, CMOS, Common-mode rejection ratio, Electrical engineering, Power supply rejection ratio, Voltage, Differential amplifier, Amplifier

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