Stability analysis of SRAM cell for energy reduction using deep sub micron technology

Low Power VLSI Circuit has great demand in present world; Power consumption is very less in CMOS circuit Design, so we built SRAM using CMOS which consume less power and have less read and write time. By fabricating millions of transistor over a single chip this decrease Device size and increase chip density of circuit. The charging and discharging of bit line and bit line is depends on barred and write operation. To enhance the power performance of the SRAM cell static noise margin (SNM) has to be improved. A SRAM cell must meet requirements for operation in sub-micron ranges. The SRAM cell random fluctuation of electrical characteristics and substantial leakage current has significant impact due to scaling of CMOS technology. The paper present dynamic 12T SRAM cell and comparing the various different SRAM cell with respect to conventional SRAM 6T & 8T in various aspects such as to verify read stability and write stability analysis POWER-curve waveform is use. Simulation results affirmed that proposed 12T SRAM cell achieved improved read and write stability, read current, and leakage current in 50nm Technology comparing with conventional SRAM 6T & 8T using tanner EDA tool 13.0.