DECIPHERING LUT FPGA CONFIGURATION OF THE FINITE STATE MACHINE WITH QUARTUSII

A field- programmable gate array (FPGA) as one of the options of programmable logic occupies an intermediate position between the hardware and software and are widely used in the development of digital equipment. FPGAs contain programmable logic components called «logic cells» or «logic element» LE and a reconfigurable interconnects. The basis of such logic elements are LUT – Look Up Table , in which loaded the truth table logic function. When this setting is also loaded matrix switching LE. Development projects sufficiently well described in available sources, but a detailed analysis of the resulting data configuration usually not considered, that is not conducive to quality training. It is believed that the company manufacturers do not disclose information about the configuration file. The article attempts to analyze the settings of logic elements (LE) from Altera system QuartusII. Created a finite state machine (FSM) through a system QuartusII. Describes the process of obtaining BDF FSM. Decrypted configuration of the LUT FPGA. The author has found that at least the functions of logic elements avai-lable for decoding by using the Map Viewer. Set configuration features LUT, for example, the order of the variables may be different. Deciphering hexadecimal settings allows professionals-engineers more thoughtful and detailed analysis of projects which can improve the training of engineers.