2003•Design, Automation, and Test in EuropeRequires access

Heterogeneous Programmable Logic Block Architectures

Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Larry Pileggi, Herman H. Schmit

Abstract

In this poster,we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and logic gates. We demonstrate that these PLBs offer significant performance and density benefits over more homogeneous PLBs.

About this research paper

What this paper is about

Why it matters

OpenAlex reports 15 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Key concepts: Programmable logic device, Multiplexer, Programmable logic array, Programmable Array Logic, Simple programmable logic device, Computer science, Logic family, Logic block