Error-tolerance memory microarchitecture via dynamic multithreading redundancy

Presented in this paper is an error-tolerance multithreaded register file microarchitecture that employs dynamic multithreading redundancy for error control. The proposed technique is based on the observation that concurrent threads may not access a register entry simultaneously. The non-overlapped register access patterns create hardware redundancy dynamically that can be exploited for error control. This significantly improves access time during error recovery. Simulation results of a generic simultaneous multithreading processor on the SPEC CPU2000 benchmark programs demonstrate 13.8% to 50.7% reduction in register read access overheads subject to 2% hardware overheads. The proposed error-tolerance memory microarchitecture features good scalability for future microprocessor generations, where soft errors are expected to get worse with semiconductor process scaling.