2007•Proceedings of the ... Conference on Parallel Architectures and Compilation Techniques/Proceedings of the Conference on Parallel Architectures and Compilation TechniquesRequires access
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José F. Duato
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Abstract
The validation buffer (VB) Microarchitecture retires instructions out of order, by substituting the classical ROB by the VB structure. The VB removes the negative effect of long latency instructions located at the ROB head, which prevent other instructions from retiring and cause frequent pipeline stalls due to lack of space in the ROB. This work analyzes different multithreading models (coarse grain, fine grain and simultaneous multithreading) and a set of different instruction fetch policies.