Fast transient ESD simulation of the NMOS protection transistor
J.R.M. Luchies, K. Verhaege, F.G. Kuper, A.J. Mouthaan, H.C. de Graaff
Abstract
J.R.M. Luchies, K. Verhaege, F.G. Kuper, A.J. Mouthaan, H.C. de Graaff
Abstract
The protective properties of NMOS transistors for the Charged Device Model have been investigated. With 2D device simulation it is shown that the base transition time is the limiting factor for CDM NMOS transistor protection. An improved compact transistor model accounting for intrinsic base resistance is presented.
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The protective properties of NMOS transistors for the Charged Device Model have been investigated. With 2D device simulation it is shown that the base transition time is the limiting factor for CDM NMOS transistor protection. An improved compact transistor model accounting for intrinsic base resistance is presented.
Key concepts: NMOS logic, Transistor, Electrostatic discharge, Transient (computer programming), Base (topology), Limiting, Materials science, MOSFET