Compact test sets for digital logic circuits

The cost of testing typically forms a significant portion of the total product cost. One of the major factors influencing the cost of testing is the size of the test sets. Reducing the test set sizes decreases the cost of testing as test application and test storage costs are lowered. This thesis presents an integrated methodology for deriving compact or small test sets for various fault models in combinational logic circuits, without compromising the fault coverage and without requiring undue computing resources. The problem of test set compaction for single stuck-at, CMOS stuck-open, single transition, and path delay fault models is addressed. Two different approaches to test compaction for single stuck-at faults are presented. A dynamic test compaction method, which performs test generation and test set compaction at the same time, is described. A set of heuristics to aid the derivation of small test sets are presented. The heuristics can be added to existing test generators without compromising the fault coverage. A complementary approach, in which test compaction is performed statically to reduce an already generated test set, is also presented. This approach can be applied to reduce the small test sets generated by the first approach or to reduce an arbitrary test set. As stuck-open and transition faults are closely related, test compaction techniques applicable to both the fault models are developed. The problem of generating small and comprehensive test sets by considering stuck-open and transition faults together is also addressed. A dynamic test compaction strategy which exploits the test compaction techniques developed for stuck-at faults, and which performs dynamic test overlap to generate small test sets, is presented. Test compaction procedures aimed at generating compact test sets for robust test generation of path delay faults are presented. A dynamic test compaction and overlap method and fault ordering heuristics are developed to generate tests that detect large numbers of faults. The test compaction techniques developed are directly applicable to multi-level circuits. In all the cases, extensive experimental results are presented to demonstrate the effectiveness of the test set compaction techniques presented.