1999•IEEE Transactions on Electron DevicesRequires access

Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

Baolei Cheng, Min Cao, Paul Vande Voorde, W. Greene, Hans Stork, Zhiping Yu, J.C.S. Woo

Abstract

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation.

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Key concepts: MOSFET, Dielectric, Materials science, Optoelectronics, Gate dielectric, Stack (abstract data type), Degradation (telecommunications), High-κ dielectric