A Design of Asynchronous Quasi-Delay Insensitive Computer

This paper proposes the self‐timed circuit design. Quasi‐delay insensitive circuit is introduced as asynchronous prototype. The designed circuit focuses on asynchronous processor design. The processor employs asynchronous system bus, asynchronous DMA controller and synchronous interfaces. The system almost completely asynchrony operation except I/O devices and memory interfaces, due to a limitation on the present time devices, the designed has been implemented on spartan‐3E FPGA no. 3S500EFG320 by partitioning each module to prevent place and routing conflict, 100‐Mhz memory frequency connected, and consumes 141, 063 equivalent gate counts. Finally, the timing details of each instruction execution are shown.