An efficient FPGA implementation of advanced encryption standard algorithm

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are highly attractive options for hardware implementations of cryptographic algorithm. This paper proposes an efficient FPGA implementation of advanced encryption standard (AES). An AES encryptor is designed and implemented in FPGA, which is shown to be more efficient than published approaches. An AES decryptor is also designed and integrated with the AES encryptor to yield a full functional AES en/decryptor. The proposed implementation is efficient and suitable for hardware-critical applications.