Compact and Efficient Encryption / Decryption Module for FPGA Implementation of AES

Hardware implementations of the Advanced Encryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. \nSeveral papers describe effcient architectures for ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Array). \nIn this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryption-only designs, fewer works studied low area encryption-only \narchitectures and only a few papers have investigated low area encryption/decryption structures. However, in practice, only a few applications need \nthroughput up to 20 Gbps while exible and low cost encryption/ decryption solutions are needed to protect sensible data, especially for embedded \nhardware applications. This contribution proposes an effcient solution to combine Rijndael encryption and decryption in one FPGA design, with a \nstrong focus on low area constraints. The proposed design into the smallest Xilinx FPGAs, deals with data streams of 208 Mbps, uses 163 slices and \n3 RAM blocks and improves by 68% the best-known similar designs in terms of ratio Throughput=Area. We also propose implementations in other FPGA \nFamilies (Xilinx Virtex-II) and comparisons with similar DES, triple-DES and AES implementations.