A Low-Power 14-Bit 2MSample/s Pipelined ADC with On-Chip 32-bit Correction Processor

: A 14-Bit 2MSample/s pipelined analog-to-digital converter (ADC) has been implemented. High-speed/high-resolution is achieved through the combination of a pipelined ADC architecture with an on-chip 32-bit micro-controller for self-calibration. A low power dissipation of 250mW is achieved on a single 5v supply. Design techniques reduce digital cross-talk errors associated with combining a high-precision analog converter with a large digital function on one common substrate. I. Introduction Applications in communications, ADSL, and high-speed imaging require high-speed high resolution analog-to-digital converters (ADC's). Portability of such systems demands low power operation. A fully monolithic 14-b, 2MSample/s Pipelined ADC, with on-chip 32-bit microcontroller consumes 250mW from a single 5v supply. Concurrent processing of analog signals gives the pipelined architecture power and/or speed advantages over flash and multistep ADC architectures. While self-calibration techniques redu...