A 2 V 250 MHz multimedia processor

This paper introduces a VLIW dual-issue RISC processor enhanced with sub-word and DSP instructions for multimedia applications. The processor core integrates 300 k transistors in an 8 mm/sup 2/ area and is implemented with 64 kB RAM onto a 6.0/spl times/6.2 mm/sup 2/ chip in a 2.O V, 0.3 /spl mu/m CMOS process. The processor exploits two modes of parallelism, dual issue instruction execution and 2-way sub-word operation, for a total of four operations per cycle and a peak sustained throughput of 1000 MOPS running at 250 MHz.