Recessed channel (RC) SOI NMOSFETs with self-aligned polysilicon gate formed on the RC region

We developed a new SOI device with a self-aligned polysilicon gate on the recessed channel region and obtained low source/drain resistance, symmetrical I/sub D/-V/sub DS/ characteristics and high breakdown voltage (BV/sub DSS/). The self-alignment was achieved in both source/drain doping and gate structure in recessed channel SOI device fabrication for the first time. The device needs no margin in layer-to-layer registration due to the self-alignment. Proposed method can be modified a little bit to be applied to 0.1 /spl mu/m or less device technology.