Efficient Bit-Parallel Multiplier for Binary Field Defind by Equally-Spaced Irreducible Polynomials

The choice of basis for representation of element in affects the efficiency of a multiplier. Among them, a multiplier using redundant representation efficiently supports trade-off between the area complexity and the time complexity since it can quickly carry out modular reduction. So time of a previous multiplier using redundant representation is faster than time of multiplier using others basis. But, the weakness of one has a upper space complexity compared to multiplier using others basis. In this paper, we propose a new efficient multiplier with consideration that polynomial exponentiation operations are frequently used in cryptographic hardwares. The proposed multiplier is suitable fer left-to-right exponentiation environment and provides efficiency between time and area complexity. And so, it has both time delay of and area complexity of (2m-1)(m+s). As a result, the proposed multiplier reduces compared to the previous multiplier using equally-spaced polynomials in area complexity. In addition, it reduces to in the time complexity.(:Time delay of one AND gate, :Time delay of one XOR gate, m:Degree of equally spaced irreducible polynomial, s:spacing factor)