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Design of a massively parallel computer using bit serial processing elements

Maurice F. Aburdene, K.S. Khouri, Jason E. Piatt, Jian-Qing Zheng

Abstract

A 1-bit serial processor designed for a parallel computer architecture is described. This processor is used to develop a massively parallel computational engine, with a single instruction-multiple data (SIMD) architecture. The computer is simulated and tested to verify its operation and to measure its performance for further development.

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Available abstract

Key concepts: Massively parallel, SIMD, Computer science, Parallel computing, Computer hardware, Parallel processing, Computer architecture