A delay improved gate level full adder design

The binary full adder module is an important element present in processor data paths. The speed of computation that can be achieved in a processor data path is usually governed by the operating speed of the basic full adder. In fact, the full adder logic forms the basis of essential arithmetic operations like multiplication and division. Even subtraction in two's complement form is realized in a straightforward fashion using a linear cascade of full adders. Three novel gate level solutions, namely XNM, XNAIMC and XAC based full adder designs were presented in our earlier work. In this article, we present a succinct description of a further delay improved version. For a 32-bit adder/subtractor module (ASM) constructed using the ripple carry configuration and incorporating the proposed XOR, OR, AND and complex gates (XOAC) based full adder, corresponding speed improvement of 18.7%, 9.4% and 2.9% was achieved over the realizations utilizing the XNM, XNAIMC and XAC based full adders respectively. Comprehensive comparison with similar implementations encompassing only different gate level full adder designs further substantiate the speed efficiency of the proposed adder, all targeting the highest speed corner of the 65nm STMicroelectronics CMOS process.