Programmable Pseudorandom Pattern Generator Based on LFSR

The testing of Integrated Circuits (ICs) is a critical process to ensure their reliability and functionality. Pseudo-random pattern generation has emerged as an effective approach to enhance IC testing, providing improved fault coverage, reduced test time, and the ability to detect hard-to-reach faults. Testing using Linear Feedback Shift Registers (LFSRs) holds paramount importance in numerous fields, encompassing digital design, communication systems, cryptography etc. The utilization of LFSRs for testing and validation purposes is driven by their efficacy in generating pseudo-random sequences that appear random but are entirely deterministic. Pseudorandom patterns can reduce test time significantly, as they can efficiently exercise the IC without the need for exhaustive test vectors. LFSRs finds extensive use in verification, acting as test pattern generators to assess circuit functionality under varying input conditions. LFSR testing finds application in Built-In Self-Test (BIST) structures. This minimizes the need for external test equipment and streamlines the testing process by detecting faults and verifying overall design performance. This aims to design and implement an n-bit programmable Pseudo Random Pattern Generator (PRPG). The circuit can generate pseudorandom patterns based on any user defined polynomials as well as structure of LFSR. The circuit can thus generate patterns for any polynomial degree n and for any structure of LFSR namely, Fibonacci, Galois, Complete or reseeding structures. The proposed circuit is designed using Verilog HDL and the implementation is carried out on Xilinx Vivado 2022.2 software. The performance parameters obtained from the synthesis resource and power utilization report of 8-bit, 16-bit and 32-bit LFSR structures are kept under comparison.