Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)

Advanced Encryption Standard (AES) is a widely used Symmetric-key algorithm. A small characteristics improvement of AES circuits can significantly affect the system's characteristics. The Substitution box (S-box) is the only nonlinear transformation of the AES algorithm, which dominates the complexity of any hardware implementation of the AES. This paper proposes an area-power and energy-efficient design of the S-box based on multiple optimizations including simplifying the input-output true table rather than the direct implementation of the Galois Field inversions GF (28) equations. The gate-level and architecture optimization of the proposed S-box reduces the area of squaring, multiplication with λ, and multiplicative inverse over the GF (24) blocks, using minimum number of XOR gates. The power, area, and power-delay product (PDP) improvement in the selected technologies, 90nm, 45nm, and 32 nm are, respectively; 18-75%, 18-31%, and 30-60%, accounting for a respective improvement of AES, when compared with conventional S-box substituted AES block.