A Comprehensive SPICE Modeling Methodology for Hot-carrier Degradation

Defect generation and subsequent performance degradation due to hot carriers is one the main reliability issues in the CMOS technologies. Although hot-carrier degradation (HCD) has been studied and modeled extensively, most of the proposed modeling methodologies have focused on analytical modeling of electrical (ET) parameters. To simulate the effects of HCD on circuit performance, SPICE based modeling is imperative. This – more often than not – is a challenging feat because most of the standard SPICE models do not include reliability physics. This paper presents an accurate methodology for implementing HCD in SPICE models, tested across various CMOS technologies and standard SPICE models.