Efficient design of approximate adders for FPGAs

In this paper, efficient design of approximate adders to effective utilization of the FPGA resources are proposed. The designs are proposed to analyze the differences between power, area and delay in the adders. The following are the approximate adders such as low error and area efficient approximate adder (LEADx), area and power efficient approximate adder (APEx) and high speed and power efficient approximate adder (HSPEx). This type of adders consists of two parts where the least significant part represents approximate adder and most significant part represents accurate adder. The purpose of the approximate adder is to lessen the power, area and delay in the adders. LEADx and APEx has more delay compared to HSPEx approximate adder. HSPEx significantly reduces more area compared to APEx and APEx reduces more area compared to LEADx approximate adder. The HSPEx approximate adder uses the inner stage input-output pipelining technique to reduce the use of LUTs and increase the speed of the adder whereas APEx adder uses truncation technique by fixing constant 1 to some of bits in the adder. Compared to other approximate adders the HSPEx adder absorbs relatively less power. The synthetization and simulation of the proposed method is performed using Xilinx VIVADO.