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2023•Unpublished venueRequires access

A Two-Step Reconfigurable Time-to-Digital Converter Based on Gate-Vernier Rings

Tian Zhao, Kai Ma, Tao Yin, Jian Liu, Zhao Zhang, Liyuan Liu

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Abstract

Time-to-digital converter (TDC) is currently a key technology in the fields of single-photon avalanche diode (SPAD) time-resolved imaging. TDC has attracted widespread attention due to good resistance to the PVT variations and fine resolution. This paper presents a two-step reconfigurable TDC which is based on gate-vernier rings and self-biased phased-locked loop (SBPLL). The drawback of the Vernier ring oscillator is its long conversion time, So this paper proposes a reconfigurable vernier ring oscillator to meet the requirements of different dead times. The system adopts gating technique to reduce the power consumption. Designed in 180 nm CMOS standard process, the proposed TDC achieves 13.5-ps resolution, 40-ns dynamic range with 85-ns conversion time in the four-stage mode, and 26.9-ps resolution, 30ns conversion time in two-stage mode. The power consumption is 2.4 mW with 1.8 V supply voltage.

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What this paper is about

Time-to-digital converter (TDC) is currently a key technology in the fields of single-photon avalanche diode (SPAD) time-resolved imaging. TDC has attracted widespread attention due to good resistance to the PVT variations and fine resolution. This paper presents a two-step reconfigurable TDC which is based on gate-vernier rings and self-biased phased-locked loop (SBPLL). The drawback of the Vernier ring oscillator is its long conversion time, So this paper proposes a reconfigurable vernier ring oscillator to meet the requirements of different dead times. The system adopts gating technique to reduce the power consumption. Designed in 180 nm CMOS standard process, the proposed TDC achieves 13.5-ps resolution, 40-ns dynamic range with 85-ns conversion time in the four-stage mode, and 26.9-ps resolution, 30ns conversion time in two-stage mode. The power consumption is 2.4 mW with 1.8 V supply voltage.

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Available abstract

Time-to-digital converter (TDC) is currently a key technology in the fields of single-photon avalanche diode (SPAD) time-resolved imaging. TDC has attracted widespread attention due to good resistance to the PVT variations and fine resolution. This paper presents a two-step reconfigurable TDC which is based on gate-vernier rings and self-biased phased-locked loop (SBPLL). The drawback of the Vernier ring oscillator is its long conversion time, So this paper proposes a reconfigurable vernier ring oscillator to meet the requirements of different dead times. The system adopts gating technique to reduce the power consumption. Designed in 180 nm CMOS standard process, the proposed TDC achieves 13.5-ps resolution, 40-ns dynamic range with 85-ns conversion time in the four-stage mode, and 26.9-ps resolution, 30ns conversion time in two-stage mode. The power consumption is 2.4 mW with 1.8 V supply voltage.

Key concepts: Vernier scale, Time-to-digital converter, Ring oscillator, CMOS, Electronic engineering, Voltage, Computer science, Electrical engineering

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