2023Unpublished venueRequires access

Design and Analysis of Three-Step Cyclic Vernier Time-to-Digital Converter

Sara Mansouri, Hamidreza Rezaee-Dehsorkh, Nassim Ravanshad

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Abstract

Time-to-digital converters are one of the main and most important blocks of time-domain circuits. They are used to convert the time interval into the corresponding digital code. In this article, after an overview of the TDCs, the three-step cyclic vernier time-to-digital converter is discussed. This TDC measures the time in three steps: coarse, fine, and residue. The coarse and fine steps are performed using two digital-controlled ring oscillators. The residue step is implemented with vernier and pulse shrinking techniques. To improve the resolution and reduce the measurement error, a residue quantizer block is proposed. This block is implemented with the same vernier and pulse shrinking technique, but it has a simpler structure and smaller area. The TDC is simulated in a 180 nm CMOS process with a 1.8 V supply voltage. This TDC is configured in four modes with resolution of 14,27,40, and 53 ps and a dynamic range of 156.5 ns.

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Time-to-digital converters are one of the main and most important blocks of time-domain circuits. They are used to convert the time interval into the corresponding digital code. In this article, after an overview of the TDCs, the three-step cyclic vernier time-to-digital converter is discussed. This TDC measures the time in three steps: coarse, fine, and residue. The coarse and fine steps are performed using two digital-controlled ring oscillators. The residue step is implemented with vernier and pulse shrinking techniques. To improve the resolution and reduce the measurement error, a residue quantizer block is proposed. This block is implemented with the same vernier and pulse shrinking technique, but it has a simpler structure and smaller area. The TDC is simulated in a 180 nm CMOS process with a 1.8 V supply voltage. This TDC is configured in four modes with resolution of 14,27,40, and 53 ps and a dynamic range of 156.5 ns.

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Available abstract

Time-to-digital converters are one of the main and most important blocks of time-domain circuits. They are used to convert the time interval into the corresponding digital code. In this article, after an overview of the TDCs, the three-step cyclic vernier time-to-digital converter is discussed. This TDC measures the time in three steps: coarse, fine, and residue. The coarse and fine steps are performed using two digital-controlled ring oscillators. The residue step is implemented with vernier and pulse shrinking techniques. To improve the resolution and reduce the measurement error, a residue quantizer block is proposed. This block is implemented with the same vernier and pulse shrinking technique, but it has a simpler structure and smaller area. The TDC is simulated in a 180 nm CMOS process with a 1.8 V supply voltage. This TDC is configured in four modes with resolution of 14,27,40, and 53 ps and a dynamic range of 156.5 ns.

Key concepts: Vernier scale, Time-to-digital converter, Converters, Digital electronics, Electronic engineering, CMOS, Computer science, Voltage

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